Complementary metal-oxide-semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. ULSI circuits commonly include memory devices for the storage of data.
FIG. 1 shows the basic components of a generic memory device 100. Many memory devices have an architecture similar to the memory device 100, such as static random access memories (SRAMs) and dynamic random access memories (DRAMs). External devices 104, which reside outside the memory device 100, read data from, and write data to, the memory device 100 by interfacing with the controller 102. The controller 102, in turn, operates the devices inside the memory device 100, including the row decoder 101 and column decoder 106 to read binary data from and write binary data to the memory cells 112 in the memory array 108. A memory device such as an SRAM chip may have the memory architecture of FIG. 1 with memory cells 112 such as the six transistor SRAM cell in FIG. 2. A memory device such as a DRAM chip may have the memory architecture of FIG. 1 with memory cells 112 such as the DRAM cell in FIG. 3.
Memory devices 100 typically require memory arrays 108 with millions, billions, or more memory cells 112 organized into rows 107 and columns 109. The repeated elements in FIG. 1, including rows 107, columns 109, and memory cells 112 in the rows 107 and columns 109 are symbolized with repeated dots “. . . ”.
A memory controller 102 selectively controls the data bus 114 to read from, and write to the memory cells 112 in the memory array 108. A data bus may be generally considered to include at least two circuits interconnected by one or more wires. The data bus of the prior art 114 in FIG. 1 includes a write driver 116 and a read amplifier 111 electrically connected to a column 109 of memory cells 112 by the bitline wires BL and BLB. The bitline wires BL and BLB extend along the entire length of the memory column 109 and are electrically connected to the diffusion regions of transistors (not shown) in each memory cell 112.
FIG. 4 shows the voltage waveform VBLB1 of a data bus wire BLB1 (not shown) which is not heavily loaded. FIG. 4 also shows the voltage waveform VBLB2 of a data bus wire BLB2 (not shown) which is heavily loaded. Both signals begin transitioning towards zero volts at time t0 and reach the switching threshold of Vdd/2 at time t1 and t2 respectively. The voltage waveform VBLB2 of the heavily loaded bitline wire BLB2 slowly descends toward zero volts beginning at time t0 and reaches the switching threshold of Vdd/2 at time t2, much later than the arrival of the voltage waveform VBLB1 at the same switching threshold. The difference in time required to reach the switching point between the voltage signal VBLB1 and the voltage signal BLB2 is the delay tΔ caused by the heavy loading of the wire BLB2. A data bus suffering from a slow transient such as VBLB2 in FIG. 4 will have a slower access time. The slow access time corresponds to a low operating frequency.
Therefore, what is needed is a system and method for a high-speed access architecture for semiconductor memory devices, specifically, a system and method for high-speed access architecture of large-scale semiconductor memories.